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1. WO2021007003 - MULTIPLE PLANES OF TRANSISTORS WITH DIFFERENT TRANSISTOR ARCHITECTURES TO ENHANCE 3D LOGIC AND MEMORY CIRCUITS

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[ EN ]

CLAIMS:

1. A method of microfabrication, the method comprising:

receiving a substrate having channels for gate -all-around field-effect transistor devices, the channels including vertical stacks of channels positioned adjacent to each other, in which individual channels extend horizontally between source/drain regions, wherein, in the vertical stacks of channels, at least one channel is positioned above a second channel; depositing a dielectric on the channels to a first predetermined thickness, wherein the dielectric is deposited all around a cross-section of the channels;

masking a first portion of the channels with a first etch mask, a second portion of the channels being uncovered;

removing the deposited dielectric from the second portion of the channels;

removing the first etch mask so that the channels are uncovered; and

depositing a high-k material on the channels, wherein the high-k material is deposited all around the cross-section of the channels, wherein field-effect transistors using the first portion of channels have a greater threshold voltage as compared to field-effect transistors using the second portion of the channels.

2. The method of claim 1, wherein removing deposited dielectric includes removing a second predetermined thickness of the deposited dielectric resulting in the first portion of the channels having the first predetermined thickness of dielectric and the second portion of the channels having a third predetermined thickness of dielectric, the first predetermined thickness of dielectric being greater than the third predetermined thickness of dielectric.

3. The method of claim 1, further comprising depositing an interfacial layer of dielectric all around a cross-section of the channels subsequent to removing the first etch mask and prior to depositing the high-k material.

4. The method of claim 1, further comprising selecting the high-k material from the group including Hf02, A1203, Y203 and Zr02.

5. The method of claim 1, further comprising depositing work function metal layers subsequent to depositing the high-k material, wherein the work function metal layers include a first work function metal layer of titanium nitride, TiN, and a second work function metal layer of tantalum nitride, TaN, wherein the TaN layer is deposited over the TiN layer.

6. The method of claim 5, further comprising depositing a third work function metal layer of titanium oxy nitride, TiON, over the TaN layer.

7. The method of claim 5, further comprising depositing a third work function metal layer of titanium carbide, TiC, over the TaN layer.

8. The method of claim 5, further comprising depositing a third work function metal layer of titanium aluminum, TiAl, over the TaN layer.

9. The method of claim 5, further comprising depositing the dielectric, the high-k material and work function metals by one or more deposition methods selected from the group of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), diffusion and low pressure CVD.

10. A method of microfabrication, the method comprising:

receiving a substrate having channels for gate -all-around field-effect transistor devices, the channels including vertical stacks of channels positioned adjacent to each other in which individual channels extend horizontally between source/drain regions, wherein, in the vertical stacks of channels, at least one channel is positioned above a second channel; depositing a first layer of dielectric on the channels to a first predetermined thickness, wherein the first layer of dielectric is deposited all around a cross-section of the channels; depositing a high-k material on the channels to a first predetermined thickness of high-k material, wherein the high-k material is deposited all around a cross-section of the channels;

depositing a second layer of dielectric on the channels to a second predetermined thickness, wherein the second layer of dielectric is deposited all around a cross-section of the channels;

masking a first portion of the channels with a first etch mask, a second portion of the channels being uncovered; and

removing the second layer of dielectric from the second portion of the channels, wherein field-effect transistors using the first portion of channels have a greater threshold voltage as compared to field-effect transistors using the second portion of the channels.

11. The method of microfabrication of claim 10, further comprising removing the first etch mask.

12. The method of microfabrication of claim 10, further comprising selecting the high-k material from the group including Hf02, A1203, Y203 and Zr02.

13. The method of microfabrication of claim 10, further comprising masking the first portion of channels with the first etch mask by depositing an amorphous silicon layer over the second layer of dielectric, depositing a silicon nitride, SiN, layer over the amorphous silicon layer and depositing a resist layer over the SiN layer.

14. The method of claim 11, further comprising depositing work function metal layers subsequent to removing the first etch mask, wherein the work function metal layers include a first work function metal layer of titanium nitride, TiN, a second work function metal layer of tantalum nitride, TaN, deposited over the TiN layer and a third work function metal layer of titanium aluminum, TiAl, deposited over the TaN layer.

15. The method of claim 14, further comprising depositing the first layer of dielectric, the high-k material, the second layer of dielectric and the work function metal layers by one or more deposition methods selected from the group of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), diffusion and low pressure CVD.

16. A method of microfabrication, the method comprising:

receiving a substrate having channels for gate -all-around field-effect transistor devices, the channels including vertical stacks of channels positioned adjacent to each other in which individual channels extend horizontally between source/drain regions, wherein, in the vertical stacks of channels, at least one channel is positioned above a second channel; masking a first portion of the channels with a first etch mask, a second portion of the channels being uncovered;

executing a first plasma doping process that dopes the second portion of the channels; uncovering the first portion of the channels;

masking the second portion of the channels with a second etch mask;

executing a second plasma doping process that dopes the first portion of the channels resulting in the second portion of channels having a different threshold voltage as compared to the first portion of channels;

uncovering the second portion of the channels; and

depositing a first dielectric layer on all channels to a first predetermined thickness, wherein the first dielectric layer is deposited all around a cross-section of the channels.

17. The method of claim 16, further comprising annealing the substrate subsequent to the second plasma doping process and prior to depositing the first dielectric layer.

18. The method of claim 17, further comprising:

depositing a high-k material on the channels to a first predetermined thickness of high-k material, wherein the high-k material is deposited all around a cross-section of the channels; and

depositing a second dielectric layer on the channels to a second predetermined thickness, wherein the second dielectric layer is deposited all around a cross-section of the channels.

19. The method of claim 18, further comprising depositing work function metal layers subsequent to depositing the second dielectric layer, wherein the work function metal layers include a first work function metal layer of titanium nitride, TiN, a second work function metal layer of tantalum nitride, TaN, deposited over the TiN layer and a third work function metal layer of titanium aluminum TiAl, deposited over the TaN layer.

20. The method of microfabrication of claim 19, further comprising depositing the first dielectric layer, the high-k material, the second dielectric layer and the work function metal layers by one or more deposition methods selected from the group of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), diffusion and low pressure CVD.